[AKD4705A-A] 2007/09 - 1 - general description AKD4705A-A is an evaluation board for quickly evaluating the ak4705a, 2ch dac with av scart switch. evaluation requires audio/ video analog analyzers/generators, a di gital audio signal source, and a power supply. akm?s adc evaluation board can be al so used for the audio source. also included is a ak4112b digital audio interface receiver which receiv es s/pdif compatible audio data. the digital audio data is available via optical connector or bnc. AKD4705A-A --- ak4705a evaluation board (cable for connecting with printer port of ibm-at compatible pc and a control software are enclosed with board. this control software dose not support windows nt.) function bnc connectors for analog audio input/output bnc connectors for analog video input/output on-board clock generator bnc connector for an external clock input compatible with 2 types of digital interface 1. serial interface: direct interface with evaluat ion boards for akm?s a/d converter evaluation boards. 2. s/pdif: on-board ak4112bvf as dir that accepts optical input or bnc input 10pin header for serial control interface ak4705a tvinl monoout tvinr vcrinr vcrinl tvoutl tvoutr vcroutl vcroutr +12v +5v d5v vvd1 vvd2 v crsb vcrb v crg v crrc v crfb v crvin tvvin ency encv encc encrc encg encb tvsb rfv vcrvout tvfb vcrc tvvout tvrc tvg tvb reg . dir clock generator gnd jp9 10pin heder 10pin header control data port1 ad data rom data port3 up-i/f jp6 port2 opt in rx jp1 j1 ext jp2 ~ 5 jp10 jp11 jp8 (digital) jp12 ext j2 ext rx reg . figure 1. AKD4705A-A block diagram note 1. circuit diagram and pcb layout are attached at the end of this manual. a k4705a evaluation board rev.0 AKD4705A-A
[AKD4705A-A] 2007/09 - 2 - operation sequence 1) set up the power supply lines. name color voltage comments attention +12v orange +11.4 [v] +12.6[v] regulator, vp this jack should be always connected. +5v red +4.75[v] +5.25[v] vd this jack is open when jp9 (reg) is short. d5v red +4.75[v] +5.25[v] logic this jack is open when jp8 (d-a) is short. vvd1 red +4.75[v] vvd2 vvd1 this jack is open when jp10 (vdd1) is short. vvd2 blue vdd1 +5.25[v] vvd2 this jack is open when jp11 (vdd2) is short. agnd black 0[v] analog ground this jack should be always connected. dgnd black 0[v] digital ground this jack should be always connected. vvss2 (black 0[v] analog ground this jack should be always connected. table 1. set up of power supply lines note 2. each supply line should be distributed from the power supply unit. 2) set-up the evaluation modes, jumper pins and dip-switches. (refer next sections.) 3) connect the port3 ( p-i/f) with pc by the enclosed 10-wire flat cable. 4) set up the pc and execute the enclosed control software. (please refer to the control software manual.) 5) turn the power on. 6) reset the ak4705a once by bringing the sw1 (pdn) ?l?, and return it to ?h?.
[AKD4705A-A] 2007/09 - 3 - evaluation mode 1) s/pdif mode (optical link or bnc: default) when the cm0 (dip-switch s1_1 on board) is ?l?, the ak4112b (dir) generates mclk, bick, lrck and sdata from the received bit stream through port2 (torx 176: optical link) or j2 (bnc). this mode is used for the evaluation using cd test disk. the port1 (ext) should be open. 1)-1. dip-switch set-up no. cm0 dif2 dif0 audio data format of ak4112b notes 1 ?l? ?l? ?l? 16bit lsb justified 1 2 ?l? ?l? ?h? 18bit lsb justified 2 3 ?l? ?h? ?l? 24bit msb justified 3 4 ?l? ?h? ?h? 24bit i 2 s 4 (default) table 2. dip-switch set-up (dif1=?l?) much the data format of the ak4705a via i 2 c-bus control as following notes. note 1. 16bit lsb justified set up the dip-switch as follows. on off 12345 dif2 dif0 cm0 s1 ak4112b (reserved) (reserved) set up the control registers dif1/0 of the ak4705a by enclosed software as follows. note 2. 18bit lsb justified set up the dip-switch as follows. on off 12345 dif2 dif0 cm0 s1 ak4112b (reserved) (reserved) set up the control registers dif1/0 of the ak4705a by enclosed software as follows.
[AKD4705A-A] 2007/09 - 4 - note 3. 24bit msb justified set up the dip-switch as follows. on off 12345 dif2 dif0 cm0 s1 ak4112b (reserved) (reserved) set up the control registers dif1/0 of the ak4705a by enclosed software as follows. note 4. 24bit i 2 s (default) set up the dip-switch as follows. on off 12345 dif2 dif0 cm0 s1 ak4112b (reserved) (reserved) set up the control registers dif1/0 of the ak4705a by enclosed software as follows.
[AKD4705A-A] 2007/09 - 5 - 1)-2. jumper pins set up jp2 mclk jp3 bick jp4 sdti jp5 lrck jp1 ext (open) (default) (short) (default) (short) (default) (short) (default) (short) (default) the jp6 selects the input port of s/pdif bit stream form port2 (totx176) or j2 (bnc rx). (torx) (default) (bnc) torx bnc torx bnc jp6 rx jp6 rx
[AKD4705A-A] 2007/09 - 6 - 2) on-board x?tal mode/ feeding external mclk via bnc when the cm0 (dip-switch s1_1 on board) is ?h?, the ak4112b generates mclk, bick and lrck from on-board x?tal or external clock form j1. sdata should be fed via port1. 2)-1. dip-switch set-up no. cm0 dif2 dif0 1 ?h? don?t care don?t care table 3. dip-switch set-up (dif1=?l?) 2)-2. jumper pins set up 2)-2-a. using on-board x?tal jp2 mclk jp3 bick jp4 sdti jp5 lrck jp1 ext (open) (open) (short) (short) (short) jp6: don?t care. 2)-2-b. using external clock via bnc connector j1 jp2 mclk jp3 bick jp4 sdti jp5 lrck jp1 ext (open) (short) (short) (short) (short) jp6: don?t care. remove the on-board x?tal.
[AKD4705A-A] 2007/09 - 7 - 3) feeding all clocks from external under the following set-up, all external signals can be fed to the ak4705a thro ugh potr1 (ext). the akm?s evaluation board for adc can be used. 3)-1. dip-switch set-up no. cm0 dif2 dif0 1 don?t care don?t care don?t care table 4. dip-switch set-up (dif1=?l?) 3)-2. jumper pins set up jp2 mclk jp3 bick jp4 sdti jp5 lrck jp1 ext (open) (open) (open) (open) (open) jp6: don?t care. other jumper pins set up [jp12](vcrrc) : input jack selection for the vcrrc pin of ak4705a when the vcrc pin of the ak 4705a outputs 0v by setting cio bit to ?1?, the signal can be fed thro ugh the j27 (vcrcout) to vcrrc pin. ?i?: the signal is fed through the j18 (vcrrc) to vcrrc pin. (default) ?i/o?: the signal is fed through the j27 (vcrcout) to vcrrc pin. the cio bit of ak4705a should be set to ?1?. [jp7](gnd) : analog ground and digital ground open: separated. (default) short: connected. (the jack ?dgnd? can be open.) jp7 dgnd agnd (open) (default) jp12 i i/o i i/o jp12 (i/o) (i) (default)
[AKD4705A-A] 2007/09 - 8 - dip-switch (s1) list no. switch name default function 1 cm0 off s/p dif mode (refer the evaluation mode) 2 dif2 on 3 dif0 on 24 bit i2s mode (refer the evaluation mode) 4 - off (reserved) 5 - off (reserved) table 5. dip-switch list (dif1=?l?) jumper list no. jumper name function 1 ext mclk source set-up when cm0=?h?. open: x?tal (default). short: external clock via bnc (j1). remove the on-board x?tal. 2,3, 4,5 mclk, bick, lrck, sdti clock source set-up short: connect the dir (ak4112b). (default) open: separate the dir. supply clocks via port1. 6 rx s/pdif?s port set-up when cm0=?l?. torx: optical connector port2. (default) bnc: bnc connector j2. 7 gnd analog ground and digital ground open: separated (default). short: connected (the connector ?dgnd? can be open.). 8 d-a power supply source set-up for digital section of AKD4705A-A. open: from the ?d5v? jack. short: from the regulator or the ?+5v? jack. don?t connect anything to the ?d5v? jack. (default) 9 reg power supply source set-up for vd of ak4705a. open: from the ?+5v? jack. short: from the regulator. don?t connect anything the ?+5v? jack. (default) 10 vvd1 power supply source set-up for vvd1 of ak4705a. open: from the ?vvd1? jack. short: from the regulator or the ?+5v? jack. don?t connect anything to the ?vvd1? jack. (default) 11 vvd2 power supply source set-up for vvd1 of ak4705a. open: from the ?vvd2? jack. short: from the regulator or the ?+5v? jack. don?t connect anything to the ?vvd2? jack. (default) 12 vcrrc input selection for vcrrc ?i? side: input to vcrrc from vcrrc jack. (default) ?i/o? side: input to vcrc from vcrc jack. (note: refer cio bit of ak4705a) table 6. jumper list
[AKD4705A-A] 2007/09 - 9 - serial control the ak4705a-a can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 ( p-if ) with pc by 10 wire flat cable packed with the AKD4705A-A. be careful connector direction. flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6 pin. sda sda(ack) scl AKD4705A-A 10 pin connector 10 wire flat cable connect pc red 1 10 6 5 port3 p-if figure 2. connection of 10 pin flat cable for port3 input/output port list signal name notes input j5 (vcrinl), j3 (vcrinr), j9 (tvinl), j8 (tvinr) max: 2vrms audio output j12 (vcroutl), j10 (vcroutr), j6 (tvoutl), j7 (tvoutr), j4 (monoout) max: 3vrm digital input port2 (torx176) or j2 bnc (rx) max: d5v+0.3v input j13 (encb), j15 (encg), j17 (encrc), j19 (encc), j21 (encv), j23(ency), j25(tvvin), j14(vcrvin), j18(vcrrc; note), j20(vcrg), j22(vcrb) max: 1.5vp-p video output j27 (vcrcout; note), j29 (tvvout), j30 (tvrc), j31 (tvg), j32 (tvb), j33 (rfv), j34 (vcrvout) max: 3vp-p input j24 (vcrsb) max: vp+0.3v slow blanking output j24 (vcrsb), j28 (tvsb) max: vp input j16 (vcrfb) max: vvd1+0.3v fast blanking output j26 (tvfb) max: vvd2 table 7. input / output port list note 3. please refer to jp12 and cio bit of the ak4705a.
[AKD4705A-A] 2007/09 - 10 - the indication content for led led turns on during each output is ?h?. [le1] indicates unlock or parity error of s/pdif. connected to the erf pin of dir (ak4112b). (normally off.) [le2] indicates the validity status of s/pdif. connected to the v pin of dir (ak4112b). (normally off.) toggle switch (sw1 on board) operation ?h?: ak4705a is active. ?l?: ak4705a is powered down. note 4. when the power of AKD4705A-A is on at first, sw1 should be switched from ?l? to ?h?.
[AKD4705A-A] 2007/09 - 11 - 4) control software manual set-up of evaluation board and control software 1. set up the AKD4705A-A according to previous term. 2. connect ibm-at compatible pc with AKD4705A-A by 10-line type flat cable (packed with AKD4705A-A). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not need ed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?ak4705a evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?AKD4705A-A.exe? to set up the control program. 5. then please evaluate according to the follows. operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. 3. click ?write default? button explanation of each buttons 1. [port reset]: set up the usb interface board (akdusbif-a) when using the board. 2. [write default]: initialize the register of ak4705a. 3. [all write]: write all registers that is currently displayed. 4. [function1]: dialog to write data by keyboard operation. 5. [function2]: dialog to write data by keyboard operation. 6. [function3]: the sequence of register setting can be set and executed. 7. [function4]: the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save]: save the current register setting. 10. [open]: write the saved values to all register. 11. [write]: dialog to write data by mouse operation. indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
[AKD4705A-A] 2007/09 - 12 - explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to se t up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to the ak4705a, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexade cimal. if you want to write the input data to the ak4705a, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate datt there are dialogs corresponding to register of 02h. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to ak4705a by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to the ak4705a, click [ok] button. if not, click [cancel] button.
[AKD4705A-A] 2007/09 - 13 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the ak4705a. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.akr) and click [open] button.
[AKD4705A-A] 2007/09 - 14 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. the following is displayed. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 3. window of [f3]
[AKD4705A-A] 2007/09 - 15 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be listed up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 2 opens. figure 4. [f4] window (1)
[AKD4705A-A] 2007/09 - 16 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 3. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 5. [f4] window (2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [function4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence f ile (*.aks) should be loaded again in order to reflect the change.
[AKD4705A-A] 2007/09 - 17 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 4 opens. figure 6. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 7. [f5] windows (2) . (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
[AKD4705A-A] 2007/09 - 18 - figure 7. [f5] windows (2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displayed on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register setting file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
[AKD4705A-A] 2007/09 - 19 - revision history important notice these products and their specifications are subject to change without notice. when you consider any use or application of these product s, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. any export of these products, or devices or systems contai ning them, may require an export license or other official approval under the law and regulations of the country of ex port pertaining to customs and tariffs, currency exchange, or strategic materials. akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. it is the responsibility of the buyer or distributor of akem d products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. date (yy/mm/dd) manual revision board revision reason page contents 07/09/26 km091000 0 first edition
5 5 4 4 3 3 2 2 1 1 d d c c b b a a title size document number rev date: sheet of ak4705a 0 AKD4705A-A-48lqfp a4 11 title size document number rev date: sheet of ak4705a 0 AKD4705A-A-48lqfp a4 11 title size document number rev date: sheet of ak4705a 0 AKD4705A-A-48lqfp a4 11 (vvss) cn1 cn2 cn3 cn4 (vss) u3 + c15 10u + c15 10u r555 10k r555 10k 48 47 46 45 44 43 42 41 40 39 38 37 c18 0.1u c18 0.1u c12 0.1u c12 0.1u + c16 10u + c16 10u 36 35 34 33 32 31 30 29 28 27 26 25 c20 0.1u c20 0.1u + c21 10u + c21 10u 13 14 15 16 17 18 19 20 21 22 23 24 + c23 10u + c23 10u c14 0.1u c14 0.1u ak 4705a ak 4705a vcrc 1 vvss 2 tvvout 3 vvd2 4 tvrc 5 tvg 6 tvb 7 vvd1 8 refi 9 encb 10 encg 11 encrc 12 encc 13 encv 14 ency 15 tvvin 16 vcrvin 17 vcrfb 18 vcrrc 19 vcrg 20 vcrb 21 int 22 vcrsb 23 tvsb 24 vcrinr 25 vcrinl 26 tvinr 27 tvinl 28 vcroutr 29 vcroutl 30 tvoutr 31 tvoutl 32 monoout 33 vp 34 dvcom 35 pvcom 36 vss 37 vd 38 mclk 39 bick 40 sdti 41 lrck 42 scl 43 sda 44 pdn 45 rfv 46 vcrvout 47 tvfb 48 + c13 10u + c13 10u c17 0.1u c17 0.1u + c19 10u + c19 10u 1 2 3 4 5 6 7 8 9 10 11 12 c22 0.1u c22 0.1u -20-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a tvinr vcrc tvvin vp scl tvinl monoout vcrsb encg vvd1 vcrb vcrfb vcroutl vcrvout tvrc vcrvin vd tvb tvfb vcrinl encb intrupt vcroutr tvoutr sda mclk tvvout rfv bick encc lrck vcrinr encv encrc ency tvoutl sdti tvg tvsb vvd2 vcrrc pdn vcrg title size document number rev date: sheet of ak4705a 0 AKD4705A-A a4 26 title size document number rev date: sheet of ak4705a 0 AKD4705A-A a4 26 title size document number rev date: sheet of ak4705a 0 AKD4705A-A a4 26 (vvss2) analog ground digital ground cn1 cn2 cn3 cn4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 jp7 gnd jp7 gnd 1 2 3 4 5 6 7 8 9 10 11 12 -21-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vcrinr tvinr tvinl tvoutr vcroutr monoout tvoutl vcroutl vcrinl title size document number rev date: sheet of analog input/output circuit 0 AKD4705A-A a4 36 thursday, september 13, 2007 title size document number rev date: sheet of analog input/output circuit 0 AKD4705A-A a4 36 thursday, september 13, 2007 title size document number rev date: sheet of analog input/output circuit 0 AKD4705A-A a4 36 thursday, september 13, 2007 for analog input from analog output (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) (vvss) j7 tvoutr j7 tvoutr + c28 10u + c28 10u j4 monoout j4 monoout j12 vcroutr j12 vcroutr r20 300 r20 300 r24 300 r24 300 r27 300 r27 300 + c24 0.47u + c24 0.47u r21 (open) r21 (open) r32 300 r32 300 + c30 0.47u + c30 0.47u r28 300 r28 300 + c27 10u + c27 10u j5 vcrinl j5 vcrinl + c33 10u + c33 10u + c25 10u + c25 10u r23 300 r23 300 r30 10k r30 10k r17 (open) r17 (open) r19 300 r19 300 j3 vcrinr j3 vcrinr r25 10k r25 10k j8 tvinr j8 tvinr r16 300 r16 300 + c31 10u + c31 10u j6 tvoutl j6 tvoutl r15 300 r15 300 r22 10k r22 10k r34 10k r34 10k j10 vcroutl j10 vcroutl r26 (open) r26 (open) r18 10k r18 10k + c29 0.47u + c29 0.47u r29 (open) r29 (open) j9 tvinl j9 tvinl + c26 0.47u + c26 0.47u -22-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a encb encc encrc ency tvvin vcrb vcrfb vcrvin vcrg vcrrc encv vcrsb encg vcrcout title size document number rev date: sheet of video block input circuit 0 AKD4705A-A a4 56 title size document number rev date: sheet of video block input circuit 0 AKD4705A-A a4 56 title size document number rev date: sheet of video block input circuit 0 AKD4705A-A a4 56 i i/o (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss) (vvss) c57 0.1u c57 0.1u r79 (short) r79 (short) r70 (short) r70 (short) c58 0.1u c58 0.1u jp12 vcrrc jp12 vcrrc j14 vcrvin j14 vcrvin r75 (short) r75 (short) j20 vcrg j20 vcrg j24 vcrsb j24 vcrsb r80 (short) r80 (short) j13 encb j13 encb j16 vcrfb j16 vcrfb j21 encv j21 encv r59 75 r59 75 r51 75 r51 75 r49 75 r49 75 r57 75 r57 75 r58 10k r58 10k r50 75 r50 75 r48 75 r48 75 r46 75 r46 75 c56 0.1u c56 0.1u r54 75 r54 75 r56 300 r56 300 c50 0.1u c50 0.1u r71 (short) r71 (short) r78 300 r78 300 c51 0.1u c51 0.1u r74 (short) r74 (short) c53 0.1u c53 0.1u r55 75 r55 75 r52 75 r52 75 r81 (short) r81 (short) c52 0.1u c52 0.1u j15 encg j15 encg r72 (short) r72 (short) j25 tvvin j25 tvvin j19 encc j19 encc r53 75 r53 75 c60 0.1u c60 0.1u j17 encrc j17 encrc c55 0.1u c55 0.1u r47 75 r47 75 j23 ency j23 ency r77 (short) r77 (short) r73 (short) r73 (short) r76 (short) r76 (short) c59 0.1u c59 0.1u j18 vcrrc j18 vcrrc c54 0.1u c54 0.1u j22 vcrb j22 vcrb -23-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a tvvout tvg tvrc rfv tvb tvfb tvsb vcrvout vcrc vcrcout title size document number rev date: sheet of video block output circuit 0 AKD4705A-A a4 66 title size document number rev date: sheet of video block output circuit 0 AKD4705A-A a4 66 title size document number rev date: sheet of video block output circuit 0 AKD4705A-A a4 66 (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) (vvss2) r62 300 r62 300 j27 vcrcout j27 vcrcout j34 vcrvout j34 vcrvout j29 tvvout j29 tvvout r64 75 r64 75 j28 tvsb j28 tvsb j31 tvg j31 tvg r61 75 r61 75 j33 rfv j33 rfv j26 tvfb j26 tvfb r60 75 r60 75 r68 75 r68 75 r65 75 r65 75 j32 tvb j32 tvb r66 75 r66 75 r63 75 r63 75 j30 tvrc j30 tvrc r67 300 r67 300 -24-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a 4112b-3.3v dif2 logic sdti pdn logic logic lrck bick cm0 dif0 cm0 logic mclk dif0 4112b-3.3v logic logic dif2 intrupt title size document number rev date: sheet of ak4112b 0 AKD4705A-A a4 16 title size document number rev date: sheet of ak4112b 0 AKD4705A-A a4 16 title size document number rev date: sheet of ak4112b 0 AKD4705A-A a4 16 dif2 dif0 cm0 mclk lrck bick sdata torx bnc mclk bick sdti lrck ak4112b r5 1k r5 1k s1 sw dip-5 s1 sw dip-5 1 2 3 4 5 10 9 8 7 6 c4 0.1u c4 0.1u jp5 jp5 u2e 74hcu04 u2e 74hcu04 11 10 rp1 r-pack5r rp1 r-pack5r 5 4 3 2 1 r2 10k r2 10k jp1 ext jp1 ext port2 torx176 port2 torx176 out 1 vcc 3 gnd 4 gnd 2 6 6 5 5 r8 75 r8 75 r3 75 r3 75 ak4112bvf u1 ak4112bvf u1 tvdd 3 v/tx 4 xti 5 xto 6 pdn 7 r 8 avdd 9 avss 10 sdto 20 bick 21 daux 22 ocks0/csn 25 mck01 24 mck02 23 ocks1/cclk 26 lrck 19 rx1 11 dvss 2 dvdd 1 dif0/rx2 12 erf 18 fs96 17 cm1/cdti 27 cm0/cdto 28 dif1/rx3 13 p/s 16 auto 15 dif2/rx4 14 + c3 10u + c3 10u r1 5.1 r1 5.1 r10 100 r10 100 r4 1k r4 1k port1 ext port1 ext 1 2 3 4 5 6 7 8 9 10 r6 18k r6 18k jp3 jp3 jp2 jp2 c5 22p c5 22p r83 300 r83 300 + c1 10u + c1 10u + c7 10u + c7 10u r11 100 r11 100 c8 0.1u c8 0.1u r7 470 r7 470 le1 erf le1 erf u2f 74hcu04 u2f 74hcu04 13 12 r82 10k r82 10k r9 100 r9 100 c6 22p c6 22p + c10 10u + c10 10u jp4 jp4 c2 0.1u c2 0.1u le2 v le2 v l1 47u l1 47u r12 100 r12 100 x1 12.288mhz x1 12.288mhz 1 2 jp6 rx jp6 rx u2c 74hcu04 u2c 74hcu04 5 6 j1 bnc j1 bnc j2 bnc(rx) j2 bnc(rx) c9 0.1u c9 0.1u u2a 74hcu04 u2a 74hcu04 1 2 u2d 74hcu04 u2d 74hcu04 9 8 c11 0.1u c11 0.1u u2b 74hcu04 u2b 74hcu04 3 4 -25-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a +12v d5v +5v vvd1 vvd2 logic vp vd logic 4112b-3.3v logic sda logic logic vvd1 vvd2 logic pdn scl title size document number rev date: sheet of power supply 0 AKD4705A-A a4 46 title size document number rev date: sheet of power supply 0 AKD4705A-A a4 46 title size document number rev date: sheet of power supply 0 AKD4705A-A a4 46 for 74hct14, 74hcu04, 74ls07, 74hct541 sda(ack) scl sda(ack) sda l h l2 10u l2 10u r45 (short) r45 (short) c48 0.1u c48 0.1u u6e 74ls07 u6e 74ls07 11 10 u5f 74hct14 u5f 74hct14 13 12 u5a 74hct14 u5a 74hct14 1 2 r14 5.1 r14 5.1 c49 0.1u c49 0.1u + c46 47u + c46 47u c44 0.1u c44 0.1u u5d 74hct14 u5d 74hct14 9 8 c45 0.1u c45 0.1u + c47 47u + c47 47u + c39 47u + c39 47u r38 10k r38 10k jp9 reg jp9 reg jp8 d-a jp8 d-a r39 10k r39 10k c41 0.1u c41 0.1u t1 njm78m05fa t1 njm78m05fa out 3 gnd 2 in 1 r44 (short) r44 (short) c43 0.1u c43 0.1u u4 74hct541 u4 74hct541 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 r37 100 r37 100 u6d 74ls07 u6d 74ls07 9 8 sw1 pdn sw1 pdn r40 470 r40 470 r41 51 r41 51 + c36 47u + c36 47u u5c 74hct14 u5c 74hct14 5 6 c42 0.1u c42 0.1u r42 10k r42 10k r43 (short) r43 (short) c35 0.1u c35 0.1u u6c 74ls07 u6c 74ls07 5 6 c34 0.1u c34 0.1u jp10 vdd1 jp10 vdd1 u6b 74ls07 u6b 74ls07 3 4 t2 lp2950a t2 lp2950a out 1 gnd 2 in 3 r36 470 r36 470 port3 up-i/f port3 up-i/f 1 2 3 4 5 6 7 8 9 10 jp11 vdd2 jp11 vdd2 + c40 47u + c40 47u r13 (short) r13 (short) u6f 74ls07 u6f 74ls07 13 12 c37 0.1u c37 0.1u d1 d1 u5e 74hct14 u5e 74hct14 11 10 r35 10k r35 10k u5b 74hct14 u5b 74hct14 3 4 u6a 74ls07 u6a 74ls07 1 2 + c38 47u + c38 47u -26-
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